Computation of bus current variance for reliability estimation of VLSI circuits

This paper deals with the estimation of the median time-to-failure (MTF) due to electromigration in the power and ground busses of CMOS VLSI circuits. In our previous work [3, 4], we presented a novel technique for MTF estimation based on a stochastic current waveform model. In [6], we argued that including the variance waveform of the current, in addition to its expected waveform derived in [3, 4], would further improve the accuracy of the MTF estimate. In this paper, we present a novel technique for deriving the variance waveform for CMOS circuits. Using this technique, we establish the importance of the variance waveform by showing that its contribution to the MTF estimate can be in the range of 100% to 200% relative to that of the expected waveform. The technique has been built into the probabilistic simulator CREST [3, 4], and has shown good agreement with SPICE, as well as excellent speedup. This work was supported by Texas Instruments Inc. and the US Air Force Rome Air Development Center. yDr. Najm is now with the VLSI Design Lab., Texas Instruments Inc. MS-369, Dallas, TX. 75265. IEEE International Conference on Computer-Aided Design, 1989.